1. Field of the Invention
The present invention relates to integrated circuit (IC) technology. More specifically, the present invention pertains to fast circuits for realizing programmable interconnect architectures among circuitry on one integrated circuit, and among circuitry on different integrated circuits.
2. Prior Art
Programmable interconnect architectures are used in user-programmable arrays of logic cells, also referred to as "Field Programmable Gate Arrays (FPGAs)", as well as in dedicated programmable interconnect chips, microprocessors, digital signal processor cores, etc.
Such programmable interconnect architectures typically consist of a network of conductive nodes, programmable passive switches, and programmable or non-programmable repeater circuits. An interconnection from one conductive node to another is obtained by programming the intermediate passive switches to be conducting, and by programming each repeater circuit to be propagating and enhancing the signal from one of its terminals to another. The signal enhancement through a repeater circuit consists of driving the output with a low-impedance version of the logic signal at the input.
The repeater circuits are necessary to limit the propagation delay and the signal rise/fall time in cases where the interconnection contains many passive switches in sequence. The delay through such a network can be approximately modeled as an "RC-chain", and hence both propagation delay and rise/fall time are roughly proportional to the square of the number of switches traversed. The network of switches and repeaters can be optimized to have minimum worst case propagation delay, and an acceptable signal rise/fall time, under a given layout area constraint. The optimization consists of finding the best combination of repeater circuit sizing, switch sizing, and switch-to-repeater ratio. The switch-to-repeater ratio is the worst case number of switches between repeaters in the path of an interconnection.
The design trade-offs may be explored as follows. As the switches are made larger, their on-resistance becomes smaller, but the capacitance added to the conductive nodes becomes larger. Second order factors such as parasitic capacitance, and the non-linear voltage dependence of the on-resistance of the switches, along with the repeater sizing, must be considered to find the best switch sizing. Placing repeaters at every conductive node is possible if there is no area constraint. However, repeaters have an inherent propagation delay. When placed at every node, the repeater propagation delay dominates the total propagation delay.
In a realistic programmable interconnect architecture, a layout area constraint must be considered. In bi-directional, two-dimensional programmable interconnect architectures, such as the ones used in FPGAs, the repeater area is very large: the bi-directionality and the two-dimensionality may require a redundancy of a factor two or larger in the number of three-state buffers: not more than half the buffers, but usually fewer, are actually used when programmed. The fact that three-state buffers are employed implies large circuits and additional area overhead due to memory cells in the repeaters.
In conclusion, the area and performance of programmable bi-directional interconnect architectures may be improved efficiently by employing a bi-directional repeater circuit with a small propagation delay and a small area.
Ph.D. Dissertation "Applications of Regenerative Feedback in Integrated Circuits," by I. Dobbelaere, Stanford University, Stanford, Calif., 1995, Chapter 2, incorporated herein by reference, gives a more detailed discussion of these trade-offs.
Book "The design and analysis of VLSI circuits" by L. Glasser and D. Dobberpuhl, Addison-Wesley Publishing Company, Reading, Mass., 1985, p. 420, FIG. 8.5, shows a carry chain employing a precharge PMOS transistor and an evaluation circuit with feedback on each intermediate node of the carry chain. However, that circuit is directed to providing a short propagation delay in a dynamic logic uni-directional carry chain and it does not address the use of a delay circuits for evaluation and for postcharging in order to obtain a circuit that works independent of a clock. Finally, it does not address the use of such a circuit in a programmable interconnect architecture, and it does not address the use of such a precharge and evaluation circuit for bi-directional signal propagation.
Book "Analog VLSI and Neural Systems" by C. Mead, Chapter 12, FIG. 12.5, describes an axon repeater circuit. However, that circuit has four network nodes, is not directed to use as a single-terminal circuit for addition to intermediate nodes of an RC tree, and is not directed to use in bi-directional interconnections. Instead, it is directed to use as a stage in a unidirectional delay line using two network connections between neighboring stages.
U.S. Pat. No. 5,343,090 to R. Proebsting shows a speed enhancement technique for CMOS circuits. However, that circuit is directed towards reducing the capacitive loading in a uni-directional circuit by using a negative feedback path for postcharging a dynamic logic node, and does not address the use of a positive feedback path to enhance a transition. Furthermore, that circuit is not directed towards use for bi-directional signal propagation.